3-Stage Pipelined RISC-V CPU Written from Scratch in Verilog
For my EECS 151 final group project, we designed a pipelined RISC-V CPU in Verilog and ran it on an FPGA. It won the Apple-sponsored FPGA Outstanding Project Design Award.
Highlights
- FPGA CPU design: a pipelined RISC-V processor built from scratch, with forwarding and a branch predictor.
- Global branch prediction: adding a 5-bit global branch history raised prediction accuracy on the mmult benchmark from 78% to 96%, and lowered CPI from 1.08 to 1.05.
- Clock speed: precomputing the immediate in the fetch stage and simplifying the memory-select logic took the design from 50 MHz to 75 MHz (in the version without the global predictor).
- Memory-mapped peripherals: UART, plus cycle and instruction counters for measuring performance.
- Audio synthesizer: a fully functional, customizable audio synthesizer.